State of the art power management integrated circuits (PMICs) commonly include voltage regulators, such as LDOs, for providing stable and accurately regulated supply rails. These voltage regulators drop an input voltage by a pass device to an output voltage Vout to provide a regulated supply, free of noise. In to addition to providing static supply voltages, it may be desirable to have available dynamically controllable regulator output voltages, i.e. to have available voltage regulators that support voltage control, such as digital voltage control (DVC), for example. Such dynamic control of the regulator output voltages may be used to advantage to reduce power consumption of the overall system that include the PMIC.
Typical controllable voltage regulators (e.g., LDOs) include an error amplifier stage having an error amplifier and a buffer stage coupled (e.g. connected) in series. The error amplifier stage generates a control voltage that depends on a fixed reference voltage VREF and on a variable feedback voltage that can be adjusted for controlling the output voltage of the voltage regulator. The buffer stage receives the control voltage as an input and is thus controlled by the error amplifier stage. The buffer stage generates, as the output voltage of the voltage regulator, a voltage that depends on the control voltage.
The buffer stage in such voltage regulators typically has very high bandwidth and low output impedance to be able to drive high capacitive loads and react quickly on output load changes. On the other hand, the main loop including the error amplifier stage typically is designed for low bandwidth so as to contribute the dominant pole to the system. The output voltage of the voltage regulator may be controlled by adjusting the variable feedback voltage that is supplied to the error amplifier for comparison to the fixed reference voltage. As the buffer stage has very high bandwidth, the output voltage will follow the control voltage almost immediately. The speed with which the output voltage can be adjusted is thus determined by the bandwidth of the main loop including the error amplifier stage. Since the main loop error amplifier stage typically has low bandwidth, the change rate for the output voltage will be low as well.
The change rate of the output voltage might be increased by adding a fixed load to the output when controlling the output voltage. Adding such fixed load would increase the bias current in the error amplifier of the error amplifier stage and thus lead to a higher bandwidth of the main loop. However, since stability of the voltage regulator depends on the bias current of the error amplifier, the bandwidth of the main loop cannot be increased to values that would be required for a satisfactory change rate of the output voltage. Moreover, adding the fixed load to the output would also increase current consumption of the voltage regulator and thus decrease efficiency of the voltage regulator.